Why does a device reset when it transmits?

A device runs for an hour from a laboratory supply, then restarts when sending data from its intended battery. A multimeter still reads approximately 3.3 V. The team proposes a larger capacitor, a longer watchdog timeout, or lower radio power. Any of these changes might affect the symptom. None, by itself, establishes the cause.

The decision is what to measure to distinguish a brief energy-delivery problem from a software fault triggered by transmission. We need voltage at the IC, event timing, and reset information. Average current, successful communication for most of the day, and a single voltage reading cannot answer that question.

The following example is calculated. No board measurements were performed, and the numbers do not characterize a particular radio module. ESP32 documentation provides an example of real manufacturer guidance. The model deliberately has a simpler scope so that its arithmetic and the limits of its conclusions can be checked.

Establish what “reset” means

A device disappearing from the network does not necessarily mean that its processor restarted. It can indicate a lost connection, a stalled task, a radio-only restart, or a server problem. Confirm a complete restart through a boot counter, startup message, or another signal independent of the communication channel being investigated.

If a restart occurred, read its cause as early as possible. ESP-IDF provides esp_reset_reason(), with causes that distinguish software supervision and supply-related events. The reference is pinned to version 6.1. A product should also record firmware version and configuration, because interpretation depends on the particular chip and settings.

A reset register is evidence, not a complete oscilloscope record. A deep supply interruption may prevent some information from surviving. A watchdog event may result from stalled software, but can also follow a disturbance elsewhere. Logs sent through the radio that just stopped working may never arrive. A second, simple observation channel is valuable.

Do not disable brownout detection as a repair. The device may stop resetting while operating outside guaranteed conditions for its processor, memory, or peripherals. The objective is correct system operation, not merely the disappearance of a restart message. A diagnostic threshold and the minimum voltage for correct operation are different concepts.

Voltage has a measurement location

A schematic draws a 3.3 V rail as one node. A real board and cable contain distributed impedance: connector, trace, switch, positive-wire, and return-path resistance. A current pulse causes voltage drop even when the source maintains the correct value at its own terminals.

Measurements at the battery, regulator output, and IC pins answer three different questions. A drop at the source suggests investigating its condition and load capability. A stable source with a collapsing regulator output suggests regulation, input headroom, or current limiting. A stable regulator output with a drop at the IC points toward connections and local decoupling.

Ground is part of the circuit too. Referencing a distant ground point may include return-path drop or fail to represent the voltage actually seen by the IC. Measure the IC supply relative to its local ground. When comparing locations, understand instrument ground connections; do not create an accidental short through grounded oscilloscope terminals.

What a simple R, C, and ESR model explains

Assume an ideal 3.3 V source at the regulator output, total supply-path resistance R = 0.6 Ω, local effective capacitance C = 470 µF, and capacitor ESR of 0.08 Ω. ESR is equivalent series resistance. Current before transmission is 50 mA. During an illustrative 2 ms pulse it increases by 300 mA, reaching 350 mA.

Before the pulse, the IC sees 3.3 − 0.05 × 0.6 = 3.27 V. At steady state under the larger load, it would see 3.3 − 0.35 × 0.6 = 3.09 V. The capacitor changes how the circuit approaches that state, but does not remove the steady resistive drop. This observation is more important than the curve’s precise appearance.

For a current step ΔI, the additional voltage drop is:

D(t) = ΔI × R × [1 − R/(R + ESR) × exp(−t/((R + ESR) × C))]
V(t) = 3.3 V − 0.05 A × R − D(t)

Set D(t) = 0 for t < 0. After the pulse ends at 2 ms, add D(t − 2 ms), using superposition in this linear model. The immediate step depends on R and ESR in parallel. The time constant is (R + ESR) × C, approximately 0.320 ms here. Do not independently add the full ΔI × R and ΔI × ESR drops: current divides between the branches.

Immediately before 2 ms, the result is approximately 3.090 V. We adopt an illustrative project criterion of 3.10 V, which this variant fails. That line is neither an ESP32 brownout threshold nor a universal operating limit for electronics. A real criterion must come from every supplied component’s requirements, tolerances, conditions, and the selected margin.

Two changes produce different outcomes

Increasing effective capacitance to 2200 µF while retaining R and ESR produces approximately 3.132 V just before the pulse ends. This particular model passes the criterion for a 2 ms pulse. Under a sufficiently long load, however, voltage still approaches 3.09 V. Changing transmission duration can therefore reverse the result without changing any components.

The second variant retains 470 µF but reduces resistance to 0.15 Ω. Initial voltage is 3.2925 V and the loaded steady-state value is 3.2475 V. Immediately before 2 ms, the model is effectively at the latter value. Better connections change both the transient response and the drop under longer loads.

This does not mean that reducing resistance is always preferable to adding capacitance. A real circuit may be dominated by connection inductance, a slow regulator, or a current-limited source. Those conditions need a different model and measurements. The conclusion here is narrower: a capacitor does not repair every energy-delivery problem.

Check repeated pulses too. The plotted model starts from equilibrium at 50 mA and shows one pulse followed by recovery. With short intervals, the capacitor may not recover before the next transmission. Testing only the first packet after a long idle period can look satisfactory while retries, network scanning, or a transmission burst exposes the problem.

Why this curve cannot predict a particular board

The source is ideal. The model excludes regulator loop bandwidth, current limiting, dropout, soft start, thermal protection, and response to changing battery voltage. It also excludes connection inductance, resonances, and radiated interference. Its purpose is to distinguish mechanisms, not approve a supply design.

Effective capacitance need not equal the printed value. Account for tolerance, temperature, DC bias, and the selected technology. ESR also depends on the component and operating conditions. Both are constant assumptions here. Engineering documentation should instead derive them from the chosen component’s data or measurements under relevant conditions.

Analog Devices MT-101 explains parasitic resistance and inductance and the importance of short decoupling connections. Several capacitors with different roles may be appropriate, but selection must consider layout and manufacturer guidance. Adding capacitance symbols to a schematic does not guarantee an improvement at the pins.

TI SLVA115A, revised February 2020, describes the relationship between output-capacitor ESR and stability for particular LDO families. Regulators do not all require the same ESR range. Substituting a supposedly better, lower-ESR component without checking the regulator datasheet can change loop stability. Verify the response after the load step as well as during it.

Manufacturer guidance starts the investigation

The ESP32 supply checklist recommends a 3.3 V source capable of at least 500 mA for a single supply and describes local capacitors and increased current during transmission. That is specific guidance for this family. It does not prove that every regulator labeled 500 mA provides an adequate transient response in every assembly.

Check memory and other loads too. The processor’s permitted range may differ from that of external flash. A sensor, LED, or converter starting simultaneously can increase the pulse. A shared rail means the transmitter need not be the sole cause, even when every reset is correlated with transmission.

Attach datasheet parameters to the exact chip, module, and board revision. Changing the radio module or regulator requires reassessment. Even a manufacturer’s reference design is a starting point whose assumptions must be compared with the actual battery, connectors, temperature, and cable length.

A measurement that does not create the fault

Start with a short connection to local ground, an appropriate voltage range, and triggering on a rail drop or transmission marker. A long probe ground lead forms a loop susceptible to coupling. If moving that lead substantially changes the observed oscillation, investigate whether the trace represents the circuit or the measurement setup.

Record bandwidth, sampling, probe, attenuation, and connection method. Bandwidth limiting may help reveal a slower droop, but can remove a short pulse that matters to the IC. Compare settings and preserve raw traces. Do not choose filtering solely because it makes the result look quieter.

Current measurement also changes the circuit. A shunt and its wiring add impedance; an unsuitable insertion point can create the reset. A current probe has its own bandwidth and sensitivity limits. A problem appearing or disappearing after instrumentation is added is an observation to explain, not a reason to discard the test.

A GPIO marker identifies when software requested transmission, but may not mark actual RF activity. The radio stack may buffer the operation. Correlate several signals: software request, current, and voltage. Do not automatically assign the delay between them to one mechanism without supporting evidence.

Change one hypothesis at a time

First reproduce the fault under stable conditions and record its occurrence rate. Then change one factor: cable length, source condition, capacitance, transmit power, or packet interval. Several simultaneous changes may remove the symptom while obscuring which condition mattered.

If a shorter connection improves voltage at the IC and removes resets with the same software, the supply-impedance hypothesis gains support. If voltage stays valid within an appropriate measurement bandwidth while resets still report a watchdog cause, investigate task blocking and transmission handling. Both faults can coexist; one positive result does not close every diagnostic path.

Do not test only a fresh battery at room temperature. Choose boundaries from the product specification: source voltage, temperature, permitted cables, and operating modes. Stay within battery and instrument safety limits. The objective is a representative test inside the declared range, not an accidental destructive experiment.

Record cases that violate the voltage criterion without causing a reset. No failure in a few trials does not establish margin. If voltage falls below the requirement, the design needs explanation even when that particular specimen continues operating. Component variation across a production batch may change the result.

Time below the threshold and measurement uncertainty

Two traces with the same minimum can have different effects. One may contain a very brief spike; another may remain below the limit for much of the transmission. A supervisor has a specified time response, and individual circuits may react differently. Record both the minimum and duration of the violation, along with the method used to determine them.

This does not make a short dip automatically acceptable. First establish whether the documentation permits such an excursion and under which conditions. Without that basis, a minimum-voltage requirement cannot be replaced with an average-voltage requirement. Absence of a reset also does not prove that memory writes, sensor reads, or communication remained correct.

Consider measurement accuracy. A result of 3.105 V against a 3.100 V limit is weak evidence if probe error, offset, and reading uncertainty are comparable to the difference. A full metrology study may be unnecessary, but the decision’s resolution must be understood. A borderline case should prompt better measurement or more margin, not favorable rounding.

Keep the minimum-detection method consistent between tests. An oscilloscope’s automatic minimum over the entire record may include startup, while a manual reading covers only transmission. An apparent revision improvement can then result from changing the analysis window. Retaining the raw record and marking the assessed interval allows another person to reproduce the conclusion.

When the regulator input becomes the limit

The plot assumes a fixed 3.3 V before R. Now consider a battery whose loaded voltage approaches the regulator’s required minimum input. Even an ideal connection between regulator and processor cannot restore missing input headroom. Measure input voltage during the same pulse, rather than only checking the battery before operation begins.

Depending on topology, the limitation may involve dropout, current limiting, behavior with a depleted source, or efficiency at the operating point. These mechanisms are absent from our equation. Fitting an R-C curve to an arbitrary trace therefore does not prove the cause. If P1 also droops, extend the model or replace it with controlled regulator load testing.

After the change, repeat tests on specimens representing component tolerances. Device and repetition counts should follow risk and the study’s purpose. Ten successful transmissions on one board are useful diagnostic observations, but not statistical proof of fleet reliability. State exactly what was tested without extending the conclusion to unexamined conditions.

When a charge-balance estimate applies

The familiar approximation ΔV = ΔI × Δt / C describes an ideal capacitor discharged by a known net current for a specified duration. With 300 mA, 2 ms, and 470 µF, it gives approximately 1.28 V. That is not the result for our circuit: the source supplies an increasing share of additional current through R, so the capacitor does not supply 300 mA throughout the entire 2 ms.

Charge balance remains useful for a quick estimate when the missing current and source-response interval are explicit. Assuming no additional source current during the first 100 µs would produce approximately 64 mV of ideal-capacitance droop. ESR and other circuit elements require separate treatment. This is a different model with different conditions, not an alternative calculation of the same curve.

Record which approximation was used and why. Two engineers can calculate different required capacitances correctly while assuming different regulator contributions. Resolve that disagreement by agreeing on the source model and load waveform, rather than selecting the larger number as a substitute for understanding.

Acceptance record for the change

Acceptance should include post-pulse overshoot, oscillation, recovery time, and restart after power interruption. A larger capacitor can change inrush current or discharge time. Improving one portion of the waveform must not introduce a new problem in another operating phase.

A completed diagnosis connects symptom, mechanism, and evidence. In our model, lower resistance improves margin under sustained load, while increased capacitance helps for a limited duration. In a real device, confirm that interpretation at the IC and retest the operating range. The result is then a justified design correction with a reproducible basis.

Sources

• Analog Devices MT-101: Decoupling Techniques, Rev. 0, 03/2009; decoupling and parasitics.
• Espressif: ESP32 Schematic Checklist, source revision a727293, link checked 27 October 2026; supply guidance for this family.
• ESP-IDF: Miscellaneous System APIs, pinned version 6.1; reset-cause API.
• Texas Instruments SLVA115A: ESR, Stability, and the LDO Regulator, revision 02/2020; capacitor-dependent stability of selected LDOs.

Sources checked on 21 October 2026. Curves come from the deterministic R-C-ESR model described above. They are neither hardware measurements nor a complete regulator simulation.